1. Technical Field
The present invention relates to an adjustment apparatus, an adjustment method, and a test apparatus for adjusting signal output timing.
2. Related Art
A test apparatus for testing a semiconductor apparatus outputs a signal having a designated waveform to the device under test at a designated timing. Prior to testing, the test apparatus adjusts the signal output timing of the driver so as to enable accurate output of the waveform at the designated timing, as shown in Patent Document 1, for example. When outputting a differential signal, the test apparatus adjusts the signal output timing between a positive driver and a negative driver.
Patent Document 1: Japanese Patent Application Publication No. 2003-43124
When adjusting the signal output timing between the positive driver and the negative driver, the positive driver and the negative driver are both connected to a single comparator. The timing adjustment is performed by acquiring both the rising edge output from the positive driver and the falling edge output from the negative driver at the same timing by the one comparator.
However, the rising response and the falling response of comparators usually are not the same. As a result, when performing adjustment in the manner described above, the time difference between the rising response and the falling response of the comparator becomes a skew between the signal output timing of the positive driver and the signal output timing of the negative driver. Therefore, in order to accurately adjust the timing between the positive driver and the negative driver, a high-precision comparator must be used.